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ICS557-06
ONE TO FOUR HCSL CLOCK BUFFER
Description
The ICS557-06 is a one to four differential to HCSL (Host Clock Signal Level) clock buffer designed for use in PCI-Express applications. The device selects one of the two differential input pairs and fans out to four pairs of differential outputs. A 20-pin TSSOP package is employed to maximize board space utilization.
Features
* * * * *
Packaged in 20-pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input differential clock of up to 200 MHz (can accept LVDS, HCSL) differential pair)
* Outputs, four pairs (HCSL, 0.7 V Current mode * Jitter 100 ps (peak-to-peak) * Output skew of 50 ps * Operating frequency of 80 MHz to 200 MHz
Block Diagram
VDD 2
OE
CLKA CLKA IN1 IN1 IN2 IN2 MUX 2 to 1 CLKB CLKB CLKC CLKC CLKD CLKD 2 SEL GND PD Rr (IREF)
MDS 557-06 B I n t e gra te d C i r c u i t S y s t e m s
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525 Race Stre et, San Jo se, CA 9 5126
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ICS557-06
One to Four HCSL Clock Buffer
Pin Assignment
SEL VDDIN IN1 IN1 PD IN2 IN2 OE GND IREF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLKA CLKA CLKB CLKB GND VDD CLKC CLKC CLKD CLKD
Select table
SEL 0 1 Input Pair selected IN2/ IN2 IN1/ IN1
20-pin (173 mil) TSSOP
Pin Descriptions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
SEL VDDIN IN1 IN1 PD IN2 IN2 OE GND Rr(IREF) CLKD CLKD CLKC CLKC VDDOUT GND CLKB CLKB CLKA CLKA
Pin Type
Input Power Input Input Input Input Input Input Power Output Output Output Output Output Power Power Output Output Output Output
Pin Description
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. Connect to +3.3 V. Supply voltage for Input clocks. HCSL/LVDS true input signal 1. HCSL/LVDS complimentary input signal 1. Powers down the chip and tri-states outputs when low. Internal pull-up resistor. HCSL/LVDS true input signal 2. HCSL/LVDS complimentary input signal 2. Provides fast output on, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor outputs. Connect to ground. Precision resistor attached to this pin is connected to the internal current reference. Differential Complimentary clock. Differential True clock. Differential Complimentary clock. Differential True clock. Connect to +3.3 V. Supply Voltage for Output Clocks. Connect to ground. Differential Complimentary clock. Differential True clock. Differential Complimentary clock. True clock.
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 021705 tel (4 08) 297-1 201
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ICS557-06
One to Four HCSL Clock Buffer
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS557-06 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane.
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD and GND pairs (2,9 and 15,16) as close to the device as possible.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-06. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50, then Rr = 475 (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF.
Load Resistors RL
Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output.
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS557-06
One to Four HCSL Clock Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-06. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD, VDDA All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 5.5 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C 2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C Parameter Supply Voltage Input High Voltage
1
Symbol V VIH VIL IIL IDD IDDOE IDDPD
Conditions OE, SEL, PD OE, SEL, PD 0 < Vin < VDD 50, 2pF OE =Low No load, PD =Low Input pin capacitance Output pin capacitance CLKOUT
Min. 3.135 2.0 VSS-0.3 -5
Typ.
Max. 3.465 VDD +0.3 0.8 5 55 20 400 7 6 5
Units V V A mA mA A pF pF nH k k
Input Low Voltage1 Input Leakage Current2 Operating Supply Current
Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistor
CIN COUT LPIN ROUT RPU
3.0 110
region.
1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included.
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS557-06
One to Four HCSL Clock Buffer
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature 0 to +70C Parameter Input Frequency Output Frequency Input High Voltage Input Low Voltage Differential Input Voltages Input Offset Voltage Output High Voltage Output Low Voltage Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 Rise Time
1,2 1,2 1,2 1,2
Symbol
Conditions
Min. 80 80
Typ.
Max. 200 200
Units MHz MHz mV mV mV V mV mV mV mV ps
VIH VIL (VID) (VIS) VOH VOL
HCSL HCSL LVDS LVDS HCSL HCSL Absolute Variation over all edges
660 -150 250 1.125 660 -150 250
700 0 350 1.25 700 0 350
850 450 1.375 850 550 140
1,2
100 tOR tOF From 0.175 V to 0.525 V From 0.525 V to 0.175 V 175 175 332 344 700 700 125 Measured at crossing point 45 All outputs All outputs tSTABLE From power-up VDD=3.3 V Input differential clock to output differential clock delay measured at mid point of input levels to mid pint of output levels tSPREAD Settling period after spread change 10 10 3.0 3.0 3 50 55
ps ps ps ps % us us ms ms ns
Fall Time1,2 Rise/Fall Time Variation1,2 Skew between Outputs Duty Cycle
1,3
Output Enable Time5 Output Disable Time5 Stabilization Time Spread Change Time Input to Output Delay
1 2 3 4 5
Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%). Measurement taken from a single-ended waveform. Measurement taken from a differential waveform. Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its PD = low.
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS557-06
One to Four HCSL Clock Buffer
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
93 78 65 20
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
HCSL Output Loads
IREF =2.3 mA 6*IREF
RL 475
RL 50.2
RL 50.2
700 mV
0 tOR 0.52 V 0.175 V
500 ps
500 ps
tOF 0.52 V 0.175 V
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS557-06
One to Four HCSL Clock Buffer
Marking Diagram
20 11
Marking Diagram (Pb free)
20 11
IC S
###### YYWW 557G-06
10
IC S
###### YYWW 557G06LF
10
1
1
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" denotes Pb free package. 4. Bottom marking: (origin). Origin = country of origin if not USA.
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS557-06
One to Four HCSL Clock Buffer
Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
20
Inches Min Max
Symbol
Min
Max
E1 INDEX AREA
E
12 D
A A1 A2 b c D E E1 e L aaa
1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A2 A1
A
c
-Ce
b SEATING PLANE L
aaa C
Ordering Information
Part / Order Number
ICS557G-06 ICS557G-06T ICS557G-06LF ICS557G-06LFT
Marking
See Page 4
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 557-06 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 021705 tel (4 08) 297-1 201
w w w. i c s t . c o m

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